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Preliminary Technical Data
FEATURES
Gain set with 1 resistor per amplifier Gain = 5 to 1000 Inputs Voltage range to 150 mV below negative rail 25 nA maximum input bias current 30 nV/Hz, RTI noise @ 1 kHz Power supplies Dual supply: 2.5V to 12.5 Single supply: 3V to 25V 600 A maximum supply current
Single Supply, Rail-to-Rail, Low Cost Instrumentation Amplifier AD8223
CONNECTION DIAGRAM
-RG -IN +IN -VS
1 2 3 4 8
+RG +VS OUTPUT REF
06925-001
- + AD8223
7 6 5
Figure 1. 8-Lead SOIC (R) and 8-Lead MSOP SOIC (RM) Packages
APPLICATIONS
Low power medical instrumentation Transducer interface Thermocouple amplifiers Industrial process controls Difference amplifiers Low power data acquisition
GENERAL DESCRIPTION
The AD8223 is an integrated single-supply instrumentation amplifier that delivers rail-to-rail output swing on a single supply (+3.0 V to +25 V supplies). The AD8223 offers superior user flexibility by allowing single-gain set resistor programming, and conforming to the 8-lead industry standard pinout configuration. With no external resistor, the AD8223 is configured for G = 5 and with an external resistor, the AD8223 can be programmed for gains up to 1000. The AD8223 holds errors to a minimum by providing superior ac CMRR that increases with increasing gain. Line noise, as well as line harmonics, is rejected because the CMRR remains constant up to 200 Hz. The AD8223 has a wide input commonmode range and can amplify signals that have a common-mode voltage 150 mV below ground. Although the design of the AD8223 is optimized to operate from a single supply, the AD8223 still provides superior performance when operated from a dual voltage supply (2.5 V to 12.5 V). Low power consumption (1.5 mW at 3 V), wide supply voltage range, and rail-to-rail output swing make the AD8223 ideal for battery-powered applications. The rail-to-rail output stage maximizes the dynamic range when operating from low supply voltages. The AD8223 replaces discrete instrumentation amplifier designs and offers superior linearity, temperature stability and reliability in a minimum of space.
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2008 Analog Devices, Inc. All rights reserved.
AD8223 TABLE OF CONTENTS
Features .............................................................................................. 1 Connection Diagram ....................................................................... 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Single Supply ................................................................................. 3 Dual Supply ................................................................................... 5 Absolute Maximum Ratings............................................................ 7 ESD Caution.................................................................................. 7 Typical Performance Characteristics ............................................. 8 Theory of Operation ...................................................................... 13 Amplifier Architecture .............................................................. 13 Gain Selection ............................................................................. 13
Preliminary Technical Data
Input Voltage Range................................................................... 13 Reference Terminal .................................................................... 14 Input Protection ......................................................................... 14 RF Interference ........................................................................... 14 Ground Returns for Input Bias Currents ................................ 15 Applications Information .............................................................. 16 Basic Connection ....................................................................... 16 Differential Output .................................................................... 16 Output Buffering ........................................................................ 16 Cables........................................................................................... 16 A Single-Supply Data Acquisition System .............................. 17 Amplifying Signals with Low Common-Mode Voltage........ 17 Outline Dimensions ....................................................................... 18 Ordering Guide .......................................................................... 19
REVISION HISTORY
Rev. PrA | Page 2 of 20
Preliminary Technical Data SPECIFICATIONS
SINGLE SUPPLY
TA = 25C, single supply, VS = +5 V, and RL = 10 k, unless otherwise noted. Table 1
Parameter COMMON MODE REJECTION RATIO DC to 60 Hz with 1 k Source Imbalance G=5 G = 10 G = 100 G = 1000 NOISE Voltage Noise, 1 kHz G=5 G = 1000 RTI, 0.1 Hz to 10 Hz G=5 G = 1000 Current Noise, 1 kHz 0.1 Hz to 10 Hz VOLTAGE OFFSET Input Offset, VOSI Average TC Output Offset, VOSO Average TC Offset Referred to Input vs. Supply (PSR) G=5 G = 10 G = 100 G = 1000 INPUT CURRENT Input Bias Current Over Temperature Average Temperature Coefficient Input Offset Current Over Temperature Average Temperature Coefficient DYNAMIC RESPONSE Small Signal -3 dB Bandwidth G=5 G = 10 G = 100 G = 1000 Slew Rate Conditions VCM = 0 V to 3 V 74 80 88 88 86 92 100 100 Min AD8223A Typ Max Min AD8223B Typ Max
AD8223
Unit
dB dB dB dB
50 30 3.0 1.5 100 1.5 Total RTI Error = VOSI + VOSO/G 400 5 1000 15
50 30 3.0 1.5 100 1.5
nV/Hz nV/Hz V p-p V p-p fA/Hz pA p-p
200 3 500 10
V V/C V V/C
80 86 90 90 17 25 0.25 5 2 2.5 25 27.5
90 96 100 100 17 25 0.25 5 2 2.5 25 27.5
dB dB dB dB nA nA pA/C nA nA pA/C
200 190 75 8 0.3
200 190 75 8 0.3
kHz kHz kHz kHz V/s
Rev. PrA | Page 3 of 20
AD8223
Parameter Settling Time to 0.01% G=5 G = 100 G = 1000 GAIN Gain Range Gain Error1 G=5 G = 10 G = 100 G = 1000 Nonlinearity G = 5 to 1000 Gain vs. Temperature G=5 G > 51 INPUT Input Impedance Differential Common-Mode Input Voltage Range2 OUTPUT Output Swing Conditions Step size = 3.5 V Min AD8223A Typ Max
Preliminary Technical Data
Min AD8223B Typ Max Unit s s s G = 5 + (80 k/RG) 5 VOUT = 0.05 V to 4.5 V 0.03 0.10 0.10 0.10 VOUT = 0.05 V to 4.5 V 50 5 50 10 50 5 50 10 ppm ppm/C ppm/C 0.15 1 1 1 0.03 0.10 0.10 0.10 0.1 0.5 0.5 0.5 % % % % 1000 5 1000 V/V
2||2 2||2 (-VS) - 0.15 RL = 10 k to ground RL = 100 k to ground +0.01 +0.01 (+VS) - 1.5 (+VS) - 0.5 (+VS) - 0.2 60 +50 -VS 1 0.0002 +3.0 +25 550 +85 +3.0 20% +60 +VS (-VS) - 0.15 +0.01 +0.01
2||2 2||2 (+VS) - 1.5 (+VS) - 0.5 (+VS) - 0.2 60 +50 -VS 1 0.0002 +25 550 +85 20% +60 +VS
G||pF G||pF V
V V
REFERENCE INPUT RIN IIN Voltage Range Gain to Output POWER SUPPLY Operating Range Quiescent Current TEMPERATURE RANGE For Specified Performance
1 2
VIN+, VREF = 0
k A V V
V A C
-40
-40
Does not include effects of external resistor RG. One input grounded. G = 1.
Rev. PrA | Page 4 of 20
Preliminary Technical Data
DUAL SUPPLY
TA = 25C, dual supply, VS = 12 V, and RL = 10 k, unless otherwise noted. Table 2.
Parameter COMMON MODE REJECTION RATIO DC to 60 Hz with 1 k Source Imbalance G=5 G = 10 G = 100 G = 1000 NOISE Voltage Noise, 1 kHz G=5 G = 1000 RTI, 0.1 Hz to 10 Hz G=5 G = 1000 Current Noise, 1 kHz 0.1 Hz to 10 Hz VOLTAGE OFFSET Input Offset, VOSI Average TC Output Offset, VOSO Average TC Offset Referred to Input vs. Supply (PSR) G=5 G = 10 G = 100 G = 1000 INPUT CURRENT Input Bias Current Over Temperature Average Temperature Coefficient Input Offset Current Over Temperature Average Temperature Coefficient DYNAMIC RESPONSE Small Signal -3 dB Bandwidth G=5 G = 10 G = 100 G = 1000 Slew Rate Settling Time to 0.01% G=5 G = 100 G = 1000 Conditions VCM = -10 V to 10 V 74 80 88 88 86 92 100 100 Min AD8223A Typ Max Min AD8223B Typ Max
AD8223
Unit
dB dB dB dB
50 30 3.0 1.5 100 1.5 Total RTI Error = VOSI + VOSO/G 400 5 1000 15
50 30 3.0 1.5 100 1.5
nV/Hz nV/Hz V p-p V p-p fA/Hz pA p-p
200 3 500 10
V V/C V V/C
80 86 90 90 17 25 0.25 5 2 2.5 25 27.5
90 96 100 100 17 25 0.25 5 2 2.5 25 27.5
dB dB dB dB nA nA pA/C nA nA pA/C
200 190 75 8 0.3 Step size = 10 V 30 30 140
Rev. PrA | Page 5 of 20
200 190 75 8 0.3 30 30 140
kHz kHz kHz kHz V/s s s s
AD8223
Parameter GAIN Gain Range Gain Error1 G=5 G = 10 G = 100 G = 1000 Nonlinearity G = 5 to 1000 Gain vs. Temperature G=5 G > 51 INPUT Input Impedance Differential Common-Mode Input Voltage Range2 OUTPUT Output Swing Conditions G = 5 + (80 k/RG) VOUT = -10 V to +10 V 0.03 0.10 0.10 0.10 VOUT = -10 V to +10 V 50 5 50 10 0.15 1 1 1 Min 5 AD8223A Typ Max 1000
Preliminary Technical Data
Min 5 0.03 0.10 0.10 0.10 50 5 50 10 AD8223B Typ Max 1000 0.1 0.5 0.5 0.5 Unit V/V % % % % ppm ppm/ C ppm/ C
2||2 2||2 (-VS) - 0.15 RL = 10 k to ground RL = 100 k to ground (-VS) + 0.2 (-VS) + 0.1 60 +50 -VS 1 0.0002 2.5 12.5 600 +85 2.5 (+VS) - 1.5 (+VS) - 0.5 (+VS) - 0.2 20% +60 +VS (-VS) - 0.15 (-VS) + 0.2 (-VS) + 0.1
2||2 2||2 (+VS) - 1.5 (+VS) - 0.5 (+VS) - 0.2 60 +50 -VS 1 0.0002 12.5 600 +85 20% +60 +VS
G||pF G||pF V
V V
REFERENCE INPUT RIN IIN Voltage Range Gain to Output POWER SUPPLY Operating Range Quiescent Current TEMPERATURE RANGE For Specified Performance
1 2
VIN+, VREF = 0
k A V V
V A C
-40
-40
Does not include effects of external resistor RG. One input grounded. G = 1.
Rev. PrA | Page 6 of 20
Preliminary Technical Data ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Supply Voltage Internal Power Dissipation Differential Input Voltage Output Short-Circuit Duration Storage Temperature Range (R, RM) Operating Temperature Range (A) Lead Temperature (Soldering 10 sec) Rating 12.5 V 650 mW 6 V Indefinite -65C to +125C -40C to +85C +300C
AD8223
THERMAL RESISTANCE
JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Specification is for device in free air. Table 4. Thermal Resistance
Package Type 8-Lead SOIC 8-Lead MSOP JA 155 200 Unit C/W C/W
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
Rev. PrA | Page 7 of 20
AD8223 TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25C VS = 5 V, RL = 10 k, unless otherwise noted.
50
Preliminary Technical Data
40 35
40
30
NUMBER OF UNITS NUMBER OF UNITS
30
25 20 15 10
20
10
06925-003 06925-006
5 0 -9 -6 -3 0 3 6 9 CMRR, G = 100 (V/V)
0 -200
-150
-100
-50
0
50
100
150
200
INPUT OFFSET VOLTAGE (V)
Figure 2. Typical Distribution of Input Offset Voltage
Figure 5. Typical Distribution for CMRR (G = 100)
80 70 60 50 40 30 20
06925-004
1000
VOLTAGE NOISE (nV/ Hz)
NUMBER OF UNITS
100 G=5 G = 10
0 0 3 6 9 12 15 18 21 24 INPUT BIAS CURRENT (nA)
10 0.1
1
10
100 FREQUENCY (Hz)
1k
10k
100k
Figure 3. Typical Distribution of Input Bias Current
Figure 6. Voltage Noise Spectral Density vs. Frequency
30
80
25
NUMBER OF UNITS
60
20
IBIAS (nA)
15
40
10
20
06925-005
5
06925-011
0 -40 -20 0 CMRR, G = 5 (V/V) 20 40
0 -60
-40
-20
0
20
40
60
80
100
120
140
TEMPERATURE (C)
Figure 4. Typical Distribution for CMRR (G = 5)
Figure 7. IBIAS vs. Temperature
Rev. PrA | Page 8 of 20
06925-050
10
G = 1000 BW LIMIT G = 100 BW LIMIT
Preliminary Technical Data
1k
AD8223
CURRENT NOISE (fA/ Hz)
G = 1000
100
G=5
06925-012
1
10
100 FREQUENCY (Hz)
1k
0.5V/DIV 1s/DIV
Figure 8. Current Noise Spectral Density vs. Frequency
18 16 14 VS = 12V 12
CMRR (dB) IBIAS (nA)
Figure 11. 0.1 Hz to 10 Hz RTI and RTO Voltage Noise
120 G = 1000 110
VS = 5V
VS = 2.5V
100 90 80 70 60 50
06925-013
G=5
G = 100
G = 10
10 8 6 4 2 0 -12
06925-054
10
40 30 1 10 100 1k 10k FREQUENCY (Hz)
-10
-8
-6
-4
-2
0
2
4
6
8
10
100k
CMV (V)
Figure 9. IBIAS vs. CMV
120 110
0.71pA/DIV 1s/DIV
Figure 12. CMRR vs. Frequency, 12 VS
G = 1000
100 G=5 90
CMRR (dB)
G = 100
G = 10
80 70 60 50 40
06925-056
06925-014
30 1 10 100 1k 10k FREQUENCY (Hz)
100k
Figure 10. 0.1 Hz to 10 Hz Current Noise (0.71 pA/Div)
Figure 13. CMRR vs. Frequency, VS = +5 V
Rev. PrA | Page 9 of 20
06925-055
AD8223
70 60 50 G = 1000 6 5 4
Preliminary Technical Data
VS = 5V
COMMON-MODE INPUT (V)
G = 100 40 30 20 10 0 -10 -20 -30 100 1k 10k FREQUENCY (Hz) 100k
06925-018
3 2 1 0 -1 -2 -3 -4 -5 -6 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6
06925-059
VS = 2.5V VS = +5V
GAIN (dB)
G = 10 G=5
1M
OUTPUT (V)
Figure 14. Gain vs. Frequency
6 5 4 VS = 5V
Figure 17. Common-Mode Input vs. Maximum Output Voltage, G = 100, Small Supplies
16 14 12 10 VS = 12V +VS = +15V, -VS = -5V
COMMON-MODE INPUT (V)
3 2 1 0 -1 -2 -3 -4
06925-057
COMMON-MODE INPUT (V)
8 6 4 2 0 -2 -4 -6 -8 -12 -14 -14 -12 -10 -8 -6 -4 -2 0 2 4 6 8 10 12 14 16 18
06925-060
VS = 2.5V VS = +5V
-10
-5 -6 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6
OUTPUT (V)
OUTPUT (V)
Figure 15. Common-Mode Input vs. Maximum Output Voltage, G = 5, Small Supplies
16 14 12 10 VS = 12V +VS = +15V, -VS = -5V
Figure 18. Common-Mode Input vs. Maximum Output Voltage, G = 100, Large Supplies
140
120 100 G = 1000 G = 100
COMMON-MODE INPUT (V)
8 6 4 2 0 -2 -4 -6 -8
06925-058
PSRR (dB)
80 G = 10 60 G=5 40 20 0 1 10 100 1k 10k FREQUENCY (Hz)
-12 -14 -14 -12 -10 -8 -6 -4 -2 0 2 4 6 8 10 12 14 16
100k
OUTPUT (V)
Figure 16. Common-Mode Input vs. Maximum Output Voltage, G = 5, Large Supplies
Figure 19. Positive PSRR vs. Frequency, VS = 12 V
Rev. PrA | Page 10 of 20
06925-023
-10
Preliminary Technical Data
140 120 G = 1000 G = 100 5V/DIV
AD8223
100
PSRR (dB)
80 G = 10 G=5 40 0.1%/DIV
06925-024
60
20 0 1 10 100 1k 10k FREQUENCY (Hz)
100k 100s/DIV
Figure 20. Positive PSRR vs. Frequency, VS = 5 V
120 G = 1000 100
Figure 23. Large Signal Response, G = 5
80
5V/DIV G = 100
PSRR (dB)
60 G = 10 40 G=5
20
06925-025
0.1%/DIV
1
10
100
1k
10k
100k
FREQUENCY (Hz)
100s/DIV
Figure 21. Negative PSRR vs. Frequency, VS = 12 V
Figure 24. Large Signal Pulse Response, G = 100, CL = 100 pF
5V/DIV
0.1%/DIV
100s/DIV
Figure 22. Settling Time to 0.005% vs. Gain, for a 20 V Step at Output, CL = 100 pF, VS = 12 V
Figure 25. Large Signal Pulse Response, G = 1000, CL = 100 pF
Rev. PrA | Page 11 of 20
06925-053
06925-052
0
06925-051
AD8223
+VS
Preliminary Technical Data
G=5 G = 10 G = 100
OUTPUT VOLTAGE SWING (V) REFERRED TO SUPPLY VOLTAGES
-1
-2 2
1
06925-037
2
-VS
06925-028
0.01
0.1 IOUT (mA)
1
10
20mV/DIV
10s/DIV
Figure 26. Small Signal Pulse Response, G = 5, 10, 100; RL = 10 k
Figure 28. Output Voltage Swing vs. Output Current
2
20mV/DIV
100s/DIV
Figure 27. Small Signal Pulse Response, G = 1000, RL = 25 k, CL = 100 pF
06925-034
Rev. PrA | Page 12 of 20
Preliminary Technical Data THEORY OF OPERATION
AMPLIFIER ARCHITECTURE
The AD8223 is an instrumentation amplifier based on a classic 3-op amp approach, modified to assure operation even at common-mode voltages at the negative supply rail. The architecture allows lower voltage offsets, better CMRR, and higher gain accuracy than competing instrumentation amplifiers in its class.
POSITIVE SUPPLY 7 +
AD8223
GAIN SELECTION
Placing a resistor across the RG terminals sets the gain of the AD8223, which can be calculated by referring to Table 5 or by using the following gain equation:
RG =
80 k G-5
Table 5. Gains Achieved Using 1% Resistors
1% Standard Table Value of RG () 26.7k 15.8k 5.36k 2.26k 1.78k 845 412 162 80.6 Desired Gain 8 10 20 40 50 100 200 500 1000 Calculated Gain 7.99 10.1 19.9 40.4 49.9 99.7 199 499 998
1
4
GAIN
8k 10k
8
7 -
NONINVERTING 3
+
06925-038
4 NEGATIVE SUPPLY
Figure 29. Simplified Schematic
Figure 29 shows a simplified schematic of the AD8223. The AD8223 has three stages. In the first stage, the input signal is applied to PNP transistors. These PNP transistors act as voltage buffers and allow input voltages below ground. The second stage consists of a pair of 8 k resistors, the RG resistor, and a pair of amplifiers. This stage allows the amplification of the AD8223 to be set with a single external resistor. The third stage is a differential amplifier composed of an op amp, two 10 k resistors, and two 50 k resistors. This stage removes the common mode signal and applies an additional gain of 5. The transfer function of the AD8223 is VOUT = G(VIN+ - VIN-) + VREF where:
G=5+
80 k RG
- 8k 10k 50k
INVERTING 2
- +
50k
OUT 6 REF 5
The AD8223 defaults to G = 5 when no gain resistor is used. The tolerance and gain drift of the RG resistor should be added to the specifications of the AD8223 to determine the total gain accuracy of the system. When the gain resistor is not used, gain error and gain drift are kept to a minimum.
INPUT VOLTAGE RANGE
The 3-op amp architecture of the AD8223 applies gain and then removes the common-mode voltage. Therefore, internal nodes in the AD8223 experience a combination of both the gained signal and the common-mode signal. This combined signal can be limited by the voltage supplies even when the individual input and output signals are not. To determine whether the signal can be limited, refer to Figure 15 through Figure 18. Alternatively, use the parameters in the Specifications section to verify that the input and output are not limited and then use the following formula to make sure the internal nodes are not limited: To check if it is limited by the internal nodes,
- VS + 0.01 V < 0.6 + VCM VDIFF x Gain 10 < + VS - 0.1 V
If more common-mode range is required, a solution is to apply less gain in the instrumentation amplifier and more in a later stage.
Rev. PrA | Page 13 of 20
AD8223
REFERENCE TERMINAL
The output voltage of the AD8223 is developed with respect to the potential on the reference terminal. This is useful when the output signal needs to be offset to a precise midsupply level. For example, a voltage source can be tied to the REF pin to levelshift the output so that the AD8223 can drive a single-supply ADC. The REF pin is protected with ESD diodes and should not exceed either +VS or -VS by more than 0.3 V. For best performance, source impedance to the REF terminal should be kept below 5 . As shown in Figure 29, the reference terminal, REF, is at one end of a 50 k resistor. Additional impedance at the REF terminal adds to this resistor and results in poorer CMRR performance.
INCORRECT CORRECT
Preliminary Technical Data
RF INTERFERENCE
RF rectification is often a problem when amplifiers are used in applications where there are strong RF signals. The disturbance can appear as a small dc offset voltage. High frequency signals can be filtered with a low-pass, R-C network placed at the input of the instrumentation amplifier, as shown in Figure 32. The filter limits the input signal bandwidth according to the following relationship: FilterFreqDiff = FilterFreqCM = where CD 10CC.
+15V 0.1F CC 1nF R
+
1 2 R(2CD + CC ) 1 2 RCC
AD8223
VREF VREF
AD8223
10F
+
+IN CD R1 47nF 499
+
4.02k
OP2177
-
06925-039
AD8223
-IN - REF
VOUT
R 4.02k CC 1nF
Figure 30. Driving the Reference Pin
Internal supply referenced clamping diodes allow the input, reference, output, and gain terminals of the AD8223 to safely withstand overvoltages of 0.3 V above or below the supplies. This is true for all gains, and for power-on and power-off. This last case is particularly important because the signal source and amplifier may be powered separately. If the overvoltage is expected to exceed this value, the current through these diodes should be limited to about 10 mA using external current limiting resistors. This is shown in Figure 31. The size of this resistor is defined by the supply voltage and the required overvoltage protection.
+VS RLIM VOVER RG RLIM VOVER - RLIM = -VS VOVER - VS + 0.7V
06925-040
-15V
Figure 32. RFI Suppression
Figure 32 shows an example where the differential filter frequency is approximately 400 Hz, and the common-mode filter frequency is approximately 40 kHz. The typical dc offset shift over frequency is less than 1.5 V and the circuit's RF signal rejection is better than 71 dB. The resistors were selected to be large enough to isolate the circuit's input from the capacitors, but not large enough to significantly increase the circuit's noise. Values of R and CC should be chosen to minimize RFI. Mismatch between the R x CC at the positive input and the R x CC at negative input degrades the CMRR of the AD8223. Because of their higher accuracy and stability, COG/NPO type ceramic capacitors are recommended for the CC capacitors. The dielectric for the CD capacitor is not as critical.
1 = 10mA MAX +
AD8223
OUTPUT
10mA
Figure 31. Input Protection
Rev. PrA | Page 14 of 20
06925-041
+
INPUT PROTECTION
0.1F
10F
Preliminary Technical Data
GROUND RETURNS FOR INPUT BIAS CURRENTS
Input bias currents are those dc currents that must flow to bias the input transistors of an amplifier. These are usually transistor base currents. When amplifying floating input sources such as transformers or ac-coupled sources, there must be a direct dc path into each input so that the bias current can flow. Figure 33 shows how a bias current path can be provided for the cases of transformer coupling, capacitive ac-coupling and for a thermocouple application. In dc-coupled resistive bridge applications, providing this path is generally not necessary as the bias current simply flows from the bridge supply through the bridge and into the amplifier. However, if the impedances that the two inputs see are large and differ by a large amount (>10 k), the offset current of the input stage causes dc errors proportional with the input offset voltage of the amplifier.
INCORRECT
+VS
AD8223
CORRECT
+VS
AD8223
REF
AD8223
REF
-VS TRANSFORMER +VS
-VS TRANSFORMER +VS
AD8223
REF 10M -VS THERMOCOUPLE +VS C 1 fHIGH-PASS = 2RC REF C R -VS CAPACITIVELY COUPLED C
AD8223
REF
-VS THERMOCOUPLE +VS
AD8223
C
R
AD8223
REF
-VS CAPACITIVELY COUPLED
Figure 33. Creating an IBIAS Path
Rev. PrA | Page 15 of 20
06925-042
AD8223 APPLICATIONS INFORMATION
+VS +2.5V TO +6V 0.1F + RG VIN RG RG - OUTPUT REF REF (INPUT) 0.1F 10F + VOUT VIN RG RG - + 10F + RG +VS
Preliminary Technical Data
+3V TO +12V 0.1F + 10F
OUTPUT REF
VOUT REF (INPUT)
-2.5V TO -6V -VS
06925-043
A. DUAL SUPPLY
B. SINGLE SUPPLY
Figure 34. Basic Connections
BASIC CONNECTION
Figure 34 shows the basic connection circuit for the AD8223. The +VS and -VS terminals are connected to the power supply. The supply can be either bipolar (VS = 2.5 V to 12.5 V) or single supply (-VS = 0 V, +VS = +3.0 V to +25 V). Power supplies should be capacitively decoupled close to the device's power pins. For best results, use surface-mount 0.1 F ceramic chip capacitors and 10 F electrolytic tantalum capacitors. The input voltage, which can be either single-ended (tie either -IN or +IN to ground) or differential, is amplified by the programmed gain. The output signal appears as the voltage difference between the output pin and the externally applied voltage on the REF input.
OUTPUT BUFFERING
The AD8223 is designed to drive loads of 10 k or greater. If the load is less than this value, the AD8223 output should be buffered with a precision single-supply op amp such as the OP113. This op amp can swing from 0 V to 4 V on its output while driving a load as small as 600 .
5V 0.1F 5V 0.1F + VIN RG -
AD8223
REF
+ OP113 - VOUT
06925-045
DIFFERENTIAL OUTPUT
Figure 35 shows how to create a differential output in-amp. A OP1177 op amp creates the inverted output. Because the op amp drives the AD8223 reference pin, the AD8223 can still ensure that the differential voltage is correct. Errors from the op amp or mismatched resistors are common to both outputs and are thus common mode. These common-mode errors should be rejected by the next device in the signal chain.
+IN
Figure 36. Output Buffering
CABLES
Receiving from a Cable
In many applications, shielded cables are used to minimize noise; for best CMR over frequency, the shield should be properly driven. Figure 37 shows an active guard drive that is configured to improve ac common-mode rejection by bootstrapping the capacitances of input cable shields, thus minimizing the capacitance mismatch between the inputs.
-INPUT +VS
2 1 7
AD8223
-IN REF 20k VREF
+OUT
100 AD8031
20k
- + OP1177
+INPUT
06925-044
RG 2 RG 2
AD8223
8 3 4 5
6
VOUT REFERENCE
-VS
-OUT
Figure 37. Common-Mode Shield Driver
Figure 35. Differential Output Using Op Amp
Rev. PrA | Page 16 of 20
06925-046
Preliminary Technical Data
Driving a Cable
All cables have a certain capacitance per unit length, which varies widely with cable type. The capacitive load from the cable may cause peaking in the AD8223's output response. To reduce the peaking, use a resistor between the AD8223 and the cable. Because cable capacitance and desired output response vary widely, this resistor is best determined empirically. A good starting point is 50 . The AD8232 operates at a low enough frequency that transmission line effects are rarely an issue; therefore, the resistor need not match the characteristic impedance of the cable.
AD8223
The bridge circuit is excited by a +5 V supply. The full-scale output voltage from the bridge (10 mV) therefore has a common-mode level of 2.5 V. The AD8223 removes the common-mode component and amplifies the input signal by a factor of 100 (RGAIN = 1.02 k). This results in an output signal of 1 V. To prevent this signal from running into the AD8223 ground rail, the voltage on the REF pin has to be raised to at least 1 V. In this example, the 2 V reference voltage from the AD7776 ADC is used to bias the AD8223 output voltage to 2 V 1 V. This corresponds to the input range of the ADC.
AMPLIFYING SIGNALS WITH LOW COMMONMODE VOLTAGE
Because the common-mode input range of the AD8223 extends 0.1 V below ground, it is possible to measure small differential signals that have low, or no, common-mode components. Figure 40 shows a thermocouple application where one side of the J-type thermocouple is grounded.
5V 0.1F
AD8223
(DIFF OUT)
AD8223
(SINGLE OUT)
+ J-TYPE THERMOCOUPLE
06925-047
RG 1.02k
AD8223
- REF
VOUT 2V
06925-049
Figure 38. Driving a Cable
Figure 40. Amplifying Bipolar Signals with Low Common-Mode Voltage
A SINGLE-SUPPLY DATA ACQUISITION SYSTEM
Interfacing bipolar signals to single-supply analog-to-digital converters (ADCs) presents a challenge. The bipolar signal must be mapped into the input range of the ADC. Figure 39 shows how this translation can be achieved.
5V 5V 5V 0.1F 0.1F
Over a temperature range from -200C to +200C, the J-type thermocouple delivers a voltage ranging from -7.890 mV to 10.777 mV. A programmed gain on the AD8223 of 100 (RG = 845) and a voltage on the AD8223 REF pin of 2 V results in the AD8223 output voltage ranging from 1.110 V to 3.077 V relative to ground.
AD7776
10mV RG 1.02k +
AD8223
- REF
AIN REFOUT
06925-048
REFIN
Figure 39. A Single Supply Data Acquisition System
Rev. PrA | Page 17 of 20
AD8223 OUTLINE DIMENSIONS
3.20 3.00 2.80
Preliminary Technical Data
3.20 3.00 2.80
8
5
1
5.15 4.90 4.65
4
PIN 1 0.65 BSC 0.95 0.85 0.75 0.15 0.00 0.38 0.22 SEATING PLANE 1.10 MAX 8 0 0.80 0.60 0.40
0.23 0.08
COPLANARITY 0.10
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 41. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters
5.00 (0.1968) 4.80 (0.1890)
8
5 4
4.00 (0.1574) 3.80 (0.1497)
1
6.20 (0.2441) 5.80 (0.2284)
1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) COPLANARITY 0.10 SEATING PLANE
1.75 (0.0688) 1.35 (0.0532)
0.50 (0.0196) 0.25 (0.0099) 8 0 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157)
45
0.51 (0.0201) 0.31 (0.0122)
COMPLIANT TO JEDEC STANDARDS MS-012-A A CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 42. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches)
Rev. PrA | Page 18 of 20
012407-A
Preliminary Technical Data
ORDERING GUIDE
Model AD8223AR AD8223AR-RL AD8223AR-R7 AD8223ARM AD8223ARM-RL AD8223ARM-R7 AD8223ARMZ1 AD8223ARMZ-RL1 AD8223ARMZ-R71 AD8223ARZ1 AD8223ARZ-RL1 AD8223ARZ-R71 AD8223BR AD8223BR-RL AD8223BR-R7 AD8223BRM AD8223BRM-RL AD8223BRM-R7 AD8223BRMZ1 AD8223BRMZ-RL1 AD8223BRMZ-R71 AD8223BRZ1 AD8223BRZ-RL1 AD8223BRZ-R71
1
AD8223
Package Description 8-Lead SOIC_N 8-Lead SOIC_N,13" Tape and Reel 8-Lead SOIC_N, 7" Tape and Reel 8-Lead MSOP 8-Lead MSOP, 13" Tape and Reel 8-Lead MSOP, 7" Tape and Reel 8-Lead MSOP 8-Lead MSOP, 13" Tape and Reel 8-Lead MSOP, 7" Tape and Reel 8-Lead SOIC_N 8-Lead SOIC_N, 13" Tape and Reel 8-Lead SOIC_N, 7" Tape and Reel 8-Lead SOIC_N 8-Lead SOIC_N, 13" Tape and Reel 8-Lead SOIC_N, 7" Tape and Reel 8-Lead MSOP 8-Lead MSOP, 13" Tape and Reel 8-Lead MSOP, 7" Tape and Reel 8-Lead MSOP 8-Lead MSOP, 13" Tape and Reel 8-Lead MSOP, 7" Tape and Reel 8-Lead SOIC_N 8-Lead SOIC_N, 13" Tape and Reel 8-Lead SOIC_N, 7" Tape and Reel Package Option R-8 R-8 R-8 RM-8 RM-8 RM-8 RM-8 RM-8 RM-8 R-8 R-8 R-8 R-8 R-8 R-8 RM-8 RM-8 RM-8 RM-8 RM-8 RM-8 R-8 R-8 R-8 Branding
Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C
Y0U Y0U Y0U Y0Q Y0Q Y0Q
Y0V Y0V Y0V Y0R Y0R Y0R
Z = RoHS Compliant Part.
Rev. PrA | Page 19 of 20
AD8223 NOTES
Preliminary Technical Data
(c)2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR06925-0-1/08(PrA)
Rev. PrA | Page 20 of 20

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